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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 19-5331; rev 2; 6/11 ordering information/selector guide general description the max5974_ provide control for wide-input-voltage, active-clamped, current-mode pwm, forward converters in power-over-ethernet (poe) powered device (pd) appli - cations. the max5974a/max5974c are well-suited for universal or telecom input range, while the max5974b/ max5974d also accommodate low input voltage down to 10.5v. the devices include several features to enhance supply efficiency. the aux driver recycles magnetizing cur - rent instead of wasting it in a dissipative clamp circuit. programmable dead time between the aux and main driver allows for zero-voltage switching (zvs). under light- load conditions, the devices reduce the switching fre - quency (frequency foldback) to reduce switching losses. the max5974a/max5974b feature unique circuitry to achieve output regulation without using an optocoupler, while the max5974c/max5974d utilize the traditional optocoupler feedback method. an internal error amplifier with a 1% reference is very useful in nonisolated design, eliminating the need for an external shunt regulator. the devices feature a unique feed-forward maximum duty-cycle clamp that makes the maximum clamp volt - age during transient conditions independent of the line voltage, allowing the use of a power mosfet with lower breakdown voltage. the programmable frequency dither - ing feature provides low-emi, spread-spectrum operation. the max5974_ are available in 16-pin tqfn-ep pack - ages and are rated for operation over the -40c to +85c temperature range. features s peak current-mode control, active-clamped forward pwm controller s regulation without optocoupler (max5974a/ max5974b) s internal 1% error amplifier s 100khz to 600khz programmable q 8% switching frequency, synchronization up to 1.2mhz s programmable frequency dithering for low-emi, spread-spectrum operation s programmable dead time, pwm soft-start, current slope compensation s programmable feed-forward maximum duty- cycle clamp, 80% maximum limit s frequency foldback for high-efficiency light- load operation s internal bootstrap uvlo with large hysteresis s 100a (typ) startup supply current s fast cycle-by-cycle peak current-limit, 35ns typical propagation delay s 115ns current-sense internal leading-edge blanking s output short-circuit protection with hiccup mode s reverse current limit to prevent transformer saturation due to reverse current s internal 18v zener clamp on supply input s 3mm x 3mm, lead-free, 16-pin tqfn-ep applications poe ieee ? 802.3af/at powered devices high-power pd (beyond the 802.3af/at standard) active-clamped forward dc-dc converters ip phones wireless access nodes security cameras note: all devices are specified over the -40c to +85c operating temperature range. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ieee is a registered service mark of the institute of electrical and electronics engineers, inc. evaluation kit available part top mark pin-package uvlo threshold (v) feedback mode max5974a ete+ +ahy 16 tqfn-ep* 16 sample/hold max5974b ete+ +ahz 16 tqfn-ep* 8.4 sample/hold max5974c ete+ +aia 16 tqfn-ep* 16 continuously connected max5974d ete+ +aib 16 tqfn-ep* 8.4 continuously connected
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in to gnd (v en = 0v) ........................................... -0.3v to +26v en, ndrv, auxdrv to gnd ..................... -0.3v to (v in + 0.3v) rt, dt, ffb, comp, ss, dclmp, dither/sync to gnd ................................................................. -0.3v to +6v fb to gnd (max5974a/max5974b only) .................. -6v to +6v fb to gnd (max5974c/max5974d only) .............. -0.3v to +6v cs, cssc to gnd ................................................... -0.8v to +6v pgnd to gnd ...................................................... -0.3v to +0.3v maximum input/output current (continuous) in, ndrv, auxdrv ...................................................... 100ma ndrv, auxdrv (pulsed for less than 100ns) .................. q 1a continuous power dissipation (t a = +70 n c) (note 1) 16-pin tqfn (derate 20.8mw/ n c above +70 n c) ....... 1666mw operating temperature range .......................... -40 n c to +85 n c maximum junction temperature ..................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics ( v in = 12v (for max5974a/max5974c, bring v in up to 17v for startup), v cs = v cssc = v dither/sync = v fb = v ffb = v dclmp = v gnd , v en = +2v, ndrv = auxdrv = ss = comp = unconnected, r rt = 34.8k i , r dt = 25k i , c in = 1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . junction-to-ambient thermal resistance ( b ja ) .............. 48 n c/w junction-to-case thermal resistance ( b jc ) ..................... 7 n c/w package thermal characteristics (note 1) parameter symbol conditions min typ max units undervoltage lockout/startup (in) bootstrap uvlo wakeup level v inuvr v in rising max5974a/ max5974c 15.4 16 16.5 v max5974b/ max5974d 8 8.4 8.85 bootstrap uvlo shutdown level v inuvf v in falling 6.65 7 7.35 v in clamp voltage v in_clamp i in = 2ma (sinking) 17 18.5 20 v in supply current in undervoltage lockout i start v in = +15v (for max5974a/ max5974c); v in = +7.5v (for max5974b/max5974d), when in bootstrap uvlo 100 150 f a in supply current after startup i c v in = +12v 1.8 3 ma enable (en) enable threshold v enr v en rising 1.17 1.215 1.26 v v enf v en falling 1.09 1.14 1.19 input current i en 1 f a oscillator (rt) rt bias voltage v rt 1.23 v ndrv switching frequency range f sw 100 600 khz
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 3 electrical characteristics (continued) ( v in = 12v (for max5974a/max5974c, bring v in up to 17v for startup), v cs = v cssc = v dither/sync = v fb = v ffb = v dclmp = v gnd , v en = +2v, ndrv = auxdrv = ss = comp = unconnected, r rt = 34.8k i , r dt = 25k i , c in = 1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units ndrv switching frequency accuracy -8 +8 % maximum duty cycle d max f sw = 250khz 79 80 82 % synchronization (sync) synchronization logic-high input v ih-sync 2.91 v synchronization pulse width 50 ns synchronization frequency range f syncin 1.1 x f sw 2 x f sw khz maximum duty cycle during synchronization d max x f sync / f sw % dithering ramp generator (dither) charging current v dither = 0v 45 50 55 f a discharging current v dither = 2.2v 43 50 57 f a ramps high trip point 2 v ramps low trip point 0.4 v soft-start and restart (ss) charging current i ss-ch 9.5 10 10.5 f a discharging current i ss-d v ss = 2v, normal shutdown 0.65 1.34 2 ma i ss-dh (v en < v enf or v in < v inuvf ), v ss = 2v, hiccup mode discharge for t rstrt (note 3) 1.6 2 2.4 f a discharge threshold to disable hiccup and restart v ss-dth 0.15 v minimum restart time during hiccup mode t rstrt-min 1024 clock cycles normal operating high voltage v ss-hi 5 v duty-cycle control range v ss-dmax d max (typ) = (v ss-dmax /2.43v) 0 2 v duty-cycle clamp (dclmp) dclmp input current i dclmp v dclmp = 0 to 5v -100 0 +100 na duty-cycle control range v dclmp-r v dclmp = 0.5v 73 75.4 77.5 % d max (typ) = 1 - (v dclmp / 2.43v) v dclmp = 1v 54 56 58 v dclmp = 2v 14.7 16.5 18.3 ndrv driver pulldown impedance r ndrv-n i ndrv (sinking) = 100ma 1.9 3.4 i pullup impedance r ndrv-p i ndrv (sourcing) = 50ma 4.7 8.3 i peak sink current 1 a peak source current 0.65 a fall time t ndrv-f c ndrv = 1nf 14 ns rise time t ndrv-r c ndrv = 1nf 27 ns
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 4 electrical characteristics (continued) ( v in = 12v (for max5974a/max5974c, bring v in up to 17v for startup), v cs = v cssc = v dither/sync = v fb = v ffb = v dclmp = v gnd , v en = +2v, ndrv = auxdrv = ss = comp = unconnected, r rt = 34.8k i , r dt = 25k i , c in = 1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) parameter symbol conditions min typ max units auxdrv driver pulldown impedance r aux-n i auxdrv (sinking) = 50ma 4.3 7.7 i pullup impedance r aux-p i auxdrv (sourcing) = 25ma 10.6 18.9 i peak sink current 0.5 a peak source current 0.3 a fall time t aux-f c auxdrv = 1nf 24 ns rise time t aux-r c auxdrv = 1nf 45 ns dead-time programming (dt) dt bias voltage v dt 1.215 v ndrv to auxdrv delay (dead time) t dt from ndrv falling to auxdrv falling r dt = 10k i 40 ns r dt = 100k i 300 350 410 from auxdrv rising to ndrv rising r dt = 10k i 40 ns r dt = 100k i 310 360 420 current-limit comparator (cs) cycle-by-cycle peak current-limit threshold v cs-peak 375 393 410 mv cycle-by-cycle reverse current-limit threshold v cs-rev turns auxdrv off for the remaining cycle if reverse current limit is exceeded -118 -100 -88 mv current-sense blanking time for reverse current limit t cs-blank- rev from auxdrv falling edge 115 ns number of consecutive peak current-limit events to hiccup n hiccup 8 events current-sense leading-edge blanking time t cs-blank from ndrv rising edge 115 ns propagation delay from comparator input to ndrv t pdcs from cs rising (10mv overdrive) to ndrv falling (excluding leading-edge blanking) 35 ns minimum on-time t on-min 100 150 200 ns slope compensation (cssc) slope compensation current ramp height current ramps peak added to cssc input per switching cycle 47 52 58 f a pwm comparator comparator offset voltage v pwm-os v comp - v cssc 1.35 1.7 2 v current-sense gain a cs-pwm d v comp / d v cssc (note 4) 3.1 3.33 3.6 v/v current-sense leading-edge blanking time t cssc-blank from ndrv rising edge 115 ns comparator propagation delay t pwm change in v cssc = 10mv (including internal leading-edge blanking) 150 ns
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 5 electrical characteristics (continued) ( v in = 12v (for max5974a/max5974c, bring v in up to 17v for startup), v cs = v cssc = v dither/sync = v fb = v ffb = v dclmp = v gnd , v en = +2v, ndrv = auxdrv = ss = comp = unconnected, r rt = 34.8k i , r dt = 25k i , c in = 1 f f, t a = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 2) note 2: all devices are 100% production tested at t a = +25 n c. limits over temperature are guaranteed by design. note 3: see the output short-circuit protection with hiccup mode section. note 4: the parameter is measured at the trip point of latch with v fb = 0v. gain is defined as d v comp / d v cssc for 0.15v < d v cssc < 0.25v. parameter symbol conditions min typ max units error amplifier fb reference voltage v ref v fb when i comp = 0, v comp = 2.5v max5974a/ max5974b 1.5 1.52 1.54 v max5974c/ max5974d 1.202 1.215 1.227 fb input bias current i fb v fb = 0 to 1.75v max5974a/ max5974b -250 +250 na max5974c/ max5974d -500 +100 voltage gain a eamp 80 db transconductance g m max5974a/ max5974b 1.8 2.55 3.2 ms max5974c/ max5974d 1.8 2.66 3.5 transconductance bandwidth bw open loop (typical gain = 1) -3db frequency max5974a/ max5974b 2 mhz max5974c/ max5974d 30 source current v fb = 1v, v comp = 2.5v 300 375 455 f a sink current v fb = 1.75v, v comp = 1v 300 375 455 f a frequency foldback (ffb) v csavg -to-ffb comparator gain 10 v/v ffb bias current i ffb v ffb = 0v, v cs = 0v (not in ffb mode) 26 30 33 f a ndrv switching frequency during foldback f sw-fb f sw /2 khz
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 6 typical operating characteristics ( v in = 12v (for max5974a/max5974c, bring v in up to 17v for startup), v cs = v cssc = v dither/sync = v fb = v ffb = v dclmp = v gnd , v en = 2v, ndrv = auxdrv = ss = comp = unconnected, r rt = 34.8k i , r dt = 25k i , unless otherwise noted. ) temperature (c) in uvlo wake-up level (v) 60 35 10 -15 15.8 15.9 16.0 16.1 16.2 16.3 15.7 -40 85 in uvlo wake-up level vs. temperature max5974a/b/c/d toc01 max5974a/max5974c temperature (c) in uvlo wake-up level (v) 60 35 10 -15 8.1 8.2 8.3 8.4 8.5 8.6 8.0 -40 85 in uvlo wake-up level vs. temperature max5974a/b/c/d toc02 max5974b/max5974d in uvlo shutdown level vs. temperature max5974a/b/c/d toc03 temperature (c) in uvlo shutdown level 60 35 10 -15 6.9 7.0 7.1 7.2 7.3 6.8 -40 85 en rising threshold vs. temperature max5974a/b/c/d toc04 temperature (c) en rising threshold (v) 60 35 10 -15 1.212 1.214 1.216 1.218 1.220 1.210 -40 85 en falling threshold vs. temeprature max5974a/b/c/d toc05 temperature (c) en falling threshold (v) 60 35 -15 10 1.143 1.144 1.145 1.146 1.148 1.147 1.149 1.150 1.142 -40 85 uvlo shutdown current vs. temperature max5974a/b/c/d toc06 temperature (c) uvlo current (a) 60 35 10 -15 80 100 120 140 60 -40 85 max5974a/max5974c max5974b/max5974d supply current vs. supply voltage (max5974a/max5974c) max5974a/b/c/d toc07 temperature (c) supply current (a) 18 16 14 12 10 8 6 4 2 100 1000 10,000 10 0 20 t a = -40c t a = +85c supply current vs. supply voltage (max5974b/max5974d) max5974a/b/c/d toc08 temperature (c) supply current (a) 18 16 14 12 10 8 6 4 2 100 1000 10,000 10 0 20 t a = -40c t a = +85c supply current vs. switching frequency max5974a/b/c/d toc09 switching frequency (khz) supply current (ma) 700 600 500 400 300 200 100 0.4 0.8 1.2 1.6 2.0 2.4 0 0 800
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 7 typical operating characteristics (continued) ( v in = 12v (for max5974a/max5974c, bring v in up to 17v for startup), v cs = v cssc = v dither/sync = v fb = v ffb = v dclmp = v gnd , v en = 2v, ndrv = auxdrv = ss = comp = unconnected, r rt = 34.8k i , r dt = 25k i , unless otherwise noted. ) soft-start charging current vs. temperature max5974a/b/c/d toc10 temperature (c) soft-start charging current (a) 60 35 10 -15 9.98 9.99 10.00 10.01 10.02 10.03 10.04 10.05 10.06 9.97 -40 85 switching frequency vs. r rt value max5974a/b/c/d toc11 r rt value (k ) switching frequency (khz) 100 1000 10 100 10 switching frequency vs. temperature max5974a/b/c/d toc12 temperature (c) switching frequency (khz) 60 35 -15 10 245 246 247 248 250 249 251 252 244 -40 85 frequency dithering vs. r dither max5974a/b/c/d toc13 r dither (k ) frequency dithering (%) 900 800 700 600 500 400 2 4 6 8 10 12 14 0 300 1000 maximum duty cycle vs. switching frequency max5974a/b/c/d toc14 switching frequency (khz) maximum duty cycle (%) 700 600 100 200 300 400 500 76 77 78 79 80 81 82 83 75 0 800 maximum duty cycle vs. temperature max5974a/b/c/d toc15 temperature (c) maximum duty cycle (%) 60 35 -15 10 80.3 80.4 80.5 80.6 80.8 80.7 80.9 81.0 80.2 -40 85 maximum duty cycle vs. sync frequency max5974a/b/c/d toc16 sync frequency (khz) maximum duty cycle (%) 450 400 350 300 5 10 15 20 25 30 35 40 45 0 250 500 v ss = 0.5v maximum duty cycle vs. v ss max5974a/b/c/d toc17 v ss (v) maximum duty cycle (%) 2.0 1.5 1.0 0.5 10 20 30 40 50 60 70 80 90 100 0 0 2.5 maximum duty cycle vs. v dclmp max5974a/b/c/d toc18 v dclmp (v) maximum duty cycle (%) 2.0 1.5 1.0 0.5 10 20 30 40 50 60 70 80 90 100 0 0 2.5
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 8 typical operating characteristics (continued) ( v in = 12v (for max5974a/max5974c, bring v in up to 17v for startup), v cs = v cssc = v dither/sync = v fb = v ffb = v dclmp = v gnd , v en = 2v, ndrv = auxdrv = ss = comp = unconnected, r rt = 34.8k i , r dt = 25k i , unless otherwise noted. ) dead time vs. r dt value max5974a/b/c/d toc19 r dt value (k ) dead time (ns) 90 80 20 30 40 60 50 70 50 100 150 200 250 300 350 400 0 10 100 dead time vs. temperature max5974a/b/c/d toc20 temperature (c) dead time (ns) 110 85 60 35 10 -15 90 92 94 96 98 100 102 88 -40 peak current-limit threshold vs. temperature max5974a/b/c/d toc21 temperature (c) peak current-limit threshold (mv) 60 35 10 -15 389 390 391 392 393 394 395 396 397 398 388 -40 85 reverse current-limit threshold vs. temperature max5974a/b/c/d toc22 temperature (c) reverse current-limit threshold (mv) 60 35 10 -15 -106 -105 -104 -103 -102 -101 -100 -99 -98 -97 -107 -40 85 slope compensation current vs. temperature max5974a/b/c/d toc23 temperature (c) slope compensation current (ma) 60 35 -15 10 50.5 51.0 51.5 52.0 53.0 52.5 53.5 54.0 50.0 -40 85 ndrv minimum on-time vs. temperature max5974a/b/c/d toc24 temperature (c) ndrv minimum on-time (ns) 60 35 10 -15 145 150 155 160 165 170 140 -40 85 current-sense gain vs. temperature max5974a/b/c/d toc25 temperature (c) current-sense gain (v/v) 60 35 10 -15 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 3.39 3.40 3.30 -40 85 feedback voltage vs. temperature max5974a/b/c/d toc26 temperature (c) feedback voltage (v) 60 35 10 -15 1.211 1.212 1.213 1.214 1.215 1.216 1.217 1.218 1.219 1.220 1.210 -40 85 max5974c/max5974d feedback voltage vs. temperature max5974a/b/c/d toc27 temperature (c) feedback voltage (v) 60 35 10 -15 1.517 1.518 1.519 1.520 1.521 1.522 1.516 -40 85
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 9 typical operating characteristics (continued) ( v in = 12v (for max5974a/max5974c, bring v in up to 17v for startup), v cs = v cssc = v dither/sync = v fb = v ffb = v dclmp = v gnd , v en = 2v, ndrv = auxdrv = ss = comp = unconnected, r rt = 34.8k i , r dt = 25k i , unless otherwise noted. ) transconductance vs. temperature max5974a/b/c/d toc28 temperature (c) transconductance (ms) 60 35 10 -15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 2.0 -40 85 max5974c/max5974d max5974a/max5974b transconductance histogram (max5974a/max5974b) max5974a/b/c/d toc29 transconductance (ms) n (%) 2.64 2.62 2.60 2.58 2.56 2.54 2.52 2.50 2.48 2.46 5 10 15 20 25 0 2.44 transconductance histogram (max5974c/max5974d) max5974a/b/c/d toc30 transconductance (ms) n (%) 2.76 2.74 2.72 2.70 2.68 2.66 2.64 2.62 2.60 2.58 5 10 15 20 25 0 2.56 enable response max5974a/b/c/d toc31 v en 5v/div v ndrv 10v/div v auxdrv 10v/div v out 5v/div 200s/div v ss ramp response max5974a/b/c/d toc33 10s/div v ss 2v/div v ndrv 10v/div v auxdrv 10v/div shutdown response max5974a/b/c/d toc32 100s/div v en 5v/div v ndrv 10v/div v auxdrv 10v/div v out 5v/div v dclmp ramp response max5974a/b/c/d toc34 10s/div v dclmp 2v/div v ndrv 10v/div v auxdrv 10v/div
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 10 typical operating characteristics (continued) ( v in = 12v (for max5974a/max5974c, bring v in up to 17v for startup), v cs = v cssc = v dither/sync = v fb = v ffb = v dclmp = v gnd , v en = 2v, ndrv = auxdrv = ss = comp = unconnected, r rt = 34.8k i , r dt = 25k i , unless otherwise noted. ) ndrv 10% to 90% rise time max5974a/b/c/d toc35 10ns/div v ndrv 2v/div 0ns 27.6ns ndrv 90% to 10% fall time max5974a/b/c/d toc36 10ns/div v ndrv 2v/div 0ns 13.8ns auxdrv 10% to 90% rise time max5974a/b/c/d toc37 10ns/div v auxdrv 2v/div 0ns 45.6ns auxdrv 90% to 10% fall time max5974a/b/c/d toc38 10ns/div v auxdrv 2v/div 0ns 21ns peak auxdrv current max5974a/b/c/d toc40 400ns/div i auxdrv 0.2a/div peak source current peak sink current peak ndrv current max5974a/b/c/d toc39 200ns/div i ndrv 0.5a/div peak source current peak sink current short-current behavior max5974a/b/c/d toc41 v in 5v/div 15v 5v v ndrv 10v/div v cs 500mv/div 40ms/div
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 11 pin configuration pin description 15 16 14 13 5 6 7 rt ffb 8 dt pgnd cs auxdrv 1 3 en 4 12 10 9 dclmp ss cssc gnd fb comp ep max5974a max5974b max5974c max5974d dither/ sync ndrv 2 11 in thin qfn top view + pin name function 1 dt dead-time programming resistor connection. connect resistor r dt from dt to gnd to set the desired dead time between the ndrv and auxdrv signals. see the dead time section to calculate the resistor value for a particular dead time. 2 dither/ sync frequency dithering programming or synchronization connection. for spread-spectrum frequency operation, connect a capacitor from dither to gnd and a resistor from dither to rt. to synchronize the internal oscillator to the externally applied frequency, connect dither/sync to the synchronization pulse. 3 rt switching frequency programming resistor connection. connect resistor r rt from rt to gnd to set the pwm switching frequency. see the oscillator/switching frequency section to calculate the resistor value for the desired oscillator frequency. 4 ffb frequency foldback threshold programming input. connect a resistor from ffb to gnd to set the output average current threshold below which the converter folds back the switching frequency to 1/2 of its original value. connect to gnd to disable frequency foldback. 5 comp transconductance amplifier output and pwm comparator input. comp is level shifted down and connected to the inverting input of the pwm comparator.
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 12 pin description (continued) pin name function 6 fb transconductance amplifier inverting input 7 gnd signal ground 8 cssc current sense with slope compensation input. a resistor connected from cssc to cs programs the amount of slope compensation. see the programmable slope compensation section. 9 cs current-sense input. current-sense connection for average current sense and cycle-by-cycle current limit. peak current-limit trip voltage is 400mv and reverse current-limit trip voltage is -100mv. 10 pgnd power ground. pgnd is the return path for gate-driver switching currents. 11 ndrv main switch gate-driver output 12 auxdrv pmos active clamp switch gate-driver output. auxdrv can also be used to drive a pulse transformer for synchronous flyback application. 13 in converter supply input. in has wide uvlo hysteresis, enabling the design of efficient power supplies. see the enable input section to determine if an external zener diode is required at in. 14 en enable input. the gate drivers are disabled and the device is in a low-power uvlo mode when the voltage on en is below v enf . when the voltage on en is above v enr , the device checks for other enable conditions. see the enable input section for more information about interfacing to en. 15 dclmp feed-forward maximum duty-cycle clamp programming input. connect a resistive divider between the input supply voltage dclmp and gnd. the voltage at dclmp sets the maximum duty cycle (d max ) of the converter inversely proportional to the input supply voltage, so that the mosfet remains protected during line transients. 16 ss soft-start programming capacitor connection. connect a capacitor from ss to gnd to program the soft-start period. this capacitor also determines hiccup mode current-limit restart time. a resistor from ss to gnd can also be used to set the d max below 75%. ep exposed pad. internally connected to gnd. connect to a large ground plane to maximize thermal performance. not intended as an electrical connection point.
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 13 block diagrams driver 1a/-0.65a dead-time contro l 11 ndrv ss 16 cs 9 cssc 8 comp 5 fb 6 in 13 en 14 vc pgnd driver 0.5a/-0.3a 12 auxdrv 1 dt 3 15 4 20% < d max < 80% rt dclmp ffb sync vb 30a/ 90a ndrv blanking pulse ss vc pgnd ffb comp v csavg dead time ndrv auxdrv pok oscillator driver logic reverse i lim limit turns off aux immediately peak i lim comp 400mv 2 dither / sync 7 gnd 10 pgnd vb 50a/ -50a 2v/400mv 10x q set q clr s count 8 events hiccup latch 115ns blanking 5v regulator enable 1.215v 18v pok vb thermal shutdown uvlo 115ns blanking r v ss < 150mv reverse i lim comp -100mv 2a 10a 2ma pok pwm comp r1 2 x r1 vb s/h 1.52v vb vb g m vb slope compensatio n low-power uvlo v inuvr = 16v (max5974a) v inuvr = 8.4v (max5974b) v inuvf = 7v max5974a max5974b
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 14 block diagrams (continued) driver 1a/-0.65a dead-tim e contro l 11 ndrv ss 16 cs 9 cssc 8 comp 5 fb 6 in 13 en 14 vc pgnd driver 0.5a/-0.3a 12 auxdrv 1 dt 3 15 4 20% < d max < 80% rt dclmp ffb sync vb 30a/ 90a ndrv blanking pulse ss vc pgnd ffb comp v csavg dead time ndrv auxdrv pok oscillator driver logic reverse i lim limit turns off aux immediately peak i lim comp 400mv 2 dither / sync 7 gnd 10 pgnd vb 50a/ -50a 2v/400mv 10x q set q clr s count 8 events hiccup latch 115ns blanking 5v regulator enable 1.215v pok vb thermal shutdown uvlo 115ns blanking r v ss < 150mv reverse i lim comp -100mv 2a 10a 2ma pok pwm comp r1 2 x r1 vb 1.215v vb vb g m vb slope compensatio n low-power uvlo v inuvr = 16v (max5974c) v inuvr = 8.4v (max5974d) v inuvf = 7v max5974c max5974d 18v
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 15 detailed description the max5974a/max5974b/max5974c/max5974d are optimized for controlling a 25w to 50w active-clamped, self-driven synchronous rectification forward converter in continuous-conduction mode. the main switch gate driver (ndrv) and the active-clamped switch driver (auxdrv) are sized to optimize efficiency for 25w design. the features-rich devices are ideal for poe ieee 802.3af/at-powered devices. the max5974a/max5974c offer a 16v bootstrap uvlo wake-up level with a 9v wide hysteresis. the low startup and operating currents allow the use of a smaller storage capacitor at the input without compromising startup and hold times. the max5974a/max5974c are well-suited for universal input (rectified 85v ac to 265v ac) or tele - com (-36v dc to -72v dc) power supplies. the max5974b/max5974d have a uvlo rising threshold of 8.4v and can accommodate for low-input voltage (12v dc to 24v dc) power sources such as wall adapters. power supplies designed with the max5974a/max5974c use a high-value startup resistor, r in , that charges a reservoir capacitor, c in (see the typical application circuits ). during this initial period, while the voltage is less than the internal bootstrap uvlo threshold, the device typically consumes only 100 f a of quiescent cur - rent. this low startup current and the large bootstrap uvlo hysteresis help to minimize the power dissipation across r in even at the high end of the universal ac input voltage (265v ac). feed-forward maximum duty-cycle clamping detects chang - es in line conditions and adjusts the maximum duty cycle accordingly to eliminate the clamp voltages (i.e., the main power fets drain voltage) dependence on the input voltage. for emi-sensitive applications, the programmable fre - quency dithering feature allows up to q 10% variation in the switching frequency. this spread-spectrum modula - tion technique spreads the energy of switching harmon - ics over a wider band while reducing their peaks, help - ing to meet stringent emi goals. the devices include a cycle-by-cycle current limit that turns off the main and aux drivers whenever the internally set threshold of 400mv is exceeded. eight consecutive occurrences of current-limit events trigger hiccup mode, which protects external components by halting switching for a period of time (t rstrt ) and allow - ing the overload current to dissipate in the load and body diode of the synchronous rectifier before soft-start is reattempted. the reverse current-limit feature of the devices turns the aux driver off for the remaining off period when v cs exceeds the -100mv threshold. this protects the transformer core from saturation due to excess reverse current under some extreme transient conditions. current-mode control loop the advantages of current-mode control over voltage- mode control are twofold. first, there is the feed-forward characteristic brought on by the controllers ability to adjust for variations in the input voltage on a cycle-by-cycle basis. second, the stability requirements of the current-mode controller are reduced to that of a single-pole system, unlike the double pole in voltage-mode control. the devices use a current-mode control loop where the scaled output of the error amplifier (comp) is compared to a slope-compensated current-sense signal at cssc. input clamp when the device is enabled, an internal 18v input clamp is active. during an overvoltage condition, the clamp prevents the voltage at the supply input in from rising above 18.5v (typ). when the device is disabled, the input clamp circuitry is also disabled. enable input the enable input is used to enable or disable the device. driving en low disables the device. note that the inter - nal 18v input clamp is also disabled when en is low. therefore, an external 18v zener diode is needed for certain operating conditions as described below.
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 16 uvlo on power source the enable input has an accurate threshold of 1.26v (max). for applications that require a uvlo on the power source, connect a resistive divider from the power source to en to gnd as shown in figure 1. a zener diode between in and pgnd is required to prevent the ndrv and auxdrv gate-drive voltages from exceeding 20v, the maximum allowed gate voltage of power fets. the external zener diode should clamp in the following range: z uvlo(max) 20v v v > > where v z is the zener voltage and v uvlo(max) is the maximum wakeup level (16.5v or 8.85v depending on the device version). an 18v zener diode is the best choice. design the resistive divider by first selecting the value of r en1 to be on the order of 100k. then calculate r en2 as follows: _ en(max) en2 en1 s(uvlo) en(max) v v r v v = where v en(max) is the maximum enable threshold volt - age and is equal to 1.26v and v s(uvlo) is the desired uvlo threshold for the power source, below which the device is disabled. the digital output connected to en should be capable of withstanding more than the maximum supply voltage. mcu control of enable input when using a microcontroller gpio to control the enable input, an 18v zener diode is required on in as shown in figure 2. high-voltage logic control of enable input in the case where en is externally controlled by a high- voltage open-drain/collector output (e.g., pgood indi - cator of a powered device controller), connect in to en through a resistor r en and connect en to an open-drain or open-collector output as shown in figure 3. select r en such that the voltage at in, when en is low, is less than 20v (i.e., the maximum gate voltage of the main and aux fets): en s(max) en in r v 20v r r < + where v s(max) is the maximum supply voltage. obeying this relationship eliminates the need for an external zener diode. the digital output connected to en should be capable of withstanding more than 20v. figure 1. programmable uvlo for the power source figure 2. mcu control of the enable input r in v s r en1 digital control in en 18v r en2 c in n max5974 c in 18v in r in v s in en mcu i/ o max5974_
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 17 always-on operation for always-on operation, connect en to in as shown in figure 4. no external zener diode is needed for this configuration. bootstrap undervoltage lockout the devices have an internal bootstrap uvlo that is very useful when designing high-voltage power supplies (see the block diagrams ). this allows the device to bootstrap itself during initial power-up. the max5974a/max5974c soft-start when v in exceeds the bootstrap uvlo thresh - old of v inuvr (16v typ). because the max5974b/max5974d are designed for use with low-voltage power sources such as wall adapt - ers outputting 12v to 24v, they have a lower uvlo wake-up threshold of 8.4v. startup operation the device starts up when the voltage at in exceeds 16v (max5974a/max5974c) or 8.4v (max5974b/max5974d) and the enable input voltage is greater than 1.26v. during normal operation, the voltage at in is nor - mally derived from a tertiary winding of the transformer (max5974c/max5974d). however, at startup there is no energy being delivered through the transformer; hence, a special bootstrap sequence is required. in the typical application circuits , c in charges through the startup resistor, r in , to an intermediate voltage. only 100 f a of the current supplied through r in is used by the ics, the remaining input current charges c in until v in reaches the bootstrap uvlo wake-up level. once v in exceeds this level, ndrv begins switching the n-channel mosfet and transfers energy to the second - ary and tertiary outputs. if the voltage on the tertiary output builds to higher than 7v (the bootstrap uvlo shutdown level), then startup has been accomplished and sustained operation commences. if v in drops below 7v before startup is complete, the device goes back to low-current uvlo. in this case, increase the value of c in in order to store enough energy to allow for the voltage at the tertiary winding to build up. while the max5974a/max5974b derive their input volt - age from the coupled inductor output during normal operation, the startup behavior is similar to that of the max5974c/max5974d. soft-start a capacitor from ss to gnd, c ss , programs the soft- start time. v ss controls the oscillator duty cycle during startup to provide a slow and smooth increase of the duty cycle to its steady-state value. calculate the value of c ss as follows: ss-ch ss ss i t c 2v = where i ss-ch (10 f a typ) is the current charging c ss dur - ing soft-start and t ss is the programmed soft-start time. a resistor can also be added from the ss pin to gnd to clamp v ss < 2v and, hence, program the maximum duty cycle to be less than 80% (see the duty-cycle clamping section). figure 3. high-voltage logic control of the enable input figure 4. always-on operation v s r in in en c in max5974 digital control n r en c in in en r in v s max5974_
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 18 n-channel mosfet gate driver the ndrv output drives an external n-channel mosfet. ndrv can source/sink in excess of 650ma/1000ma peak current; therefore, select a mosfet that yields acceptable conduction and switching losses. the exter - nal mosfet used must be able to withstand the maxi - mum clamp voltage. p-channel mosfet gate driver the auxdrv output drives an external p-channel mosfet with the aid of a level shifter. the level shifter consists of c aux , r aux , and d5 as shown in the typical application circuits . when auxdrv is high, c aux is recharged through d5. when auxdrv is low, the gate of the p-channel mosfet is pulled below the source by the voltage stored on c aux , turning on the pfet. add a zener diode between gate to source of the exter - nal n-channel and p-channel mosfets after the gate resistors to protect v gs from rising above its absolute maximum rating during transient condition (see the typical application circuits ). dead time dead time between the main and aux output edges allow zvs to occur, minimizing conduction losses and improv - ing efficiency. the dead time (t dt ) is applied to both leading and trailing edges of the main and aux outputs as shown in figure 5. connect a resistor between dt and gnd to set t dt to any value between 40ns and 400ns: dt dt 10k r t 40ns ? = oscillator/switching frequency the ics switching frequency is programmable between 100khz and 600khz with a resistor r rt connected between rt and gnd. use the following formula to determine the appropriate value of r rt needed to gen - erate the desired output-switching frequency (f sw ): 9 rt sw 8.7 10 r f = where f sw is the desired switching frequency. figure 5. dead time between auxdrv and ndrv blanking, t blk ndrv auxdrv dead time, t dt
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 19 figure 6. hiccup mode timing diagram peak current limit the current-sense resistor (r cs in the typical application circuits ), connected between the source of the n-channel mosfet and pgnd, sets the current limit. the current-limit comparator has a voltage trip level (v cs-peak ) of 400mv. use the following equation to cal - culate the value of r cs : cs pri 400mv r i = where i pri is the peak current in the primary side of the transformer, which also flows through the mosfet. when the voltage produced by this current (through the current-sense resistor) exceeds the current-limit com - parator threshold, the mosfet driver (ndrv) terminates the current on-cycle, within 35ns (typ). the devices implement 115ns of leading-edge blanking to ignore leading-edge current spikes. these spikes are caused by reflected secondary currents, current- discharging capacitance at the fets drain, and gate- charging current. use a small rc network for additional filtering of the leading-edge spike on the sense wave - form when needed. set the corner frequency between 10mhz and 20mhz. after the leading-edge blanking time, the device moni - tors v cs for any breaches of the peak current limit of 400mv. the duty cycle is terminated immediately when v cs exceeds 400mv. reverse current limit the devices protect the transformer against saturation due to reverse current by monitoring the voltage across r cs while the aux output is low and the p-channel fet is on. output short-circuit protection with hiccup mode when the device detects eight consecutive peak current- limit events, both ndrv and auxdrv driver outputs are turned off for a restart period, t rstrt . after t rstrt , the device undergoes soft-start. the duration of the restart period depends on the value of the capacitor at ss (c ss ). during this period, c ss is discharged with a pulldown cur - rent of i ss-dh (2 f a typ). once its voltage reaches 0.15v, the restart period ends and the device initiates a soft-start sequence. an internal counter ensures that the minimum restart period (t rstrt-min ) is 1024 clock cycles when the time required for c ss to discharge to 0.15v is less than 1024 clock cycles. figure 6 shows the behavior of the device prior and during hiccup mode. frequency foldback for high-efficiency light-load operation the frequency foldback threshold can be programmed from 0 to 20% of the full load current using a resistor from ffb to gnd. v csbl (blanked cs voltage) v cs-peak (400mv) hiccup discharge with i ss-dh v ss-dth soft-start voltage, v ss v ss-hi t rstrt t ss
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 20 when v csavg falls below v ffb , the device folds back the switching frequency to 1/2 the original value to reduce switching losses and increase the converter effi - ciency. calculate the value of r ffb as follows: load(light) cs ffb ffb 10 i r r i = where r ffb is the resistor between ffb and gnd, i load(light) is the current at light-load conditions that triggers frequency foldback, r cs is the value of the sense resistor connected between cs and pgnd, and i ffb is the current sourced from ffb to r ffb (30 f a typ). duty-cycle clamping the maximum duty cycle is determined by the lowest of three voltages: 2v, the voltage at ss (v ss ), and the voltage (2.43v - v dclmp ). the maximum duty cycle is calculated as: min max v d 2.43v = where v min = minimum (2v, v ss , 2.43v - v dclmp ). ss by connecting a resistor between ss and ground, the voltage at ss can be made to be lower than 2v. v ss is calculated as follows: ss ss ss-ch v r i = where r ss is the resistor connected between ss and gnd, and i ss-ch is the current sourced from ss to r ss (10 f a typ). dclmp to set d max using supply voltage feed-forward, connect a resistive divider between the supply voltage, dclmp, and gnd as shown in the typical application circuits. this feed-forward duty-cycle clamp ensures that the external n-channel mosfet is not stressed during sup - ply transients. v dclmp is calculated as follows: dclmp2 dclmp s dclmp1 dclmp2 r v v r r = + where r dclmp1 and r dclmp2 are the resistive divider values shown in the typical application circuits and v s is the input supply voltage. oscillator synchronization the internal oscillator can be synchronized to an external clock by applying the clock to dither/sync directly. the external clock frequency can be set anywhere between 1.1x to 2x the internal clock frequency. using an external clock increases the maximum duty cycle by a factor equal to f sync /f sw . this factor should be accounted for in setting the maximum duty cycle using any of the methods described in the duty-cycle clamping section. the formula below shows how the maximum duty cycle is affected by the external clock frequency: sync min max sw f v d 2.43v f = where v min is described in the duty-cycle clamping section, f sw is the switching frequency as set by the resistor connected between rt and gnd, and f sync is the external clock frequency. frequency dithering for spread- spectrum applications (low emi) the switching frequency of the converter can be dith - ered in a range of q 10% by connecting a capaci - tor from dither/sync to gnd, and a resistor from dither/sync to rt as shown in the typical application circuits . this results in lower emi. a current source at dither/sync charges the capaci - tor c dither to 2v at 50 f a. upon reaching this trip point, it discharges c dither to 0.4v at 50 f a. the charging and discharging of the capacitor generates a triangular waveform on dither/sync with peak levels at 0.4v and 2v and a frequency that is equal to: tri dither 50 a f c 3.2v = typically, f tri should be set close to 1khz. the resistor r dither connected from dither/sync to rt deter - mines the amount of dither as follows: rt dither r 4 %dither 3 r = where %dither is the amount of dither expressed as a percentage of the switching frequency. setting r dither to 10 x r rt generates q 10% dither.
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 21 programmable slope compensation the device generates a current ramp at cssc such that its peak is 50 f a at 80% duty cycle of the oscillator. an external resistor connected from cssc to the cs then converts this current ramp into programmable slope- compensation amplitude, which is added to the current- sense signal for stability of the peak current-mode control loop. the ramp rate of the slope compensation signal is given by: cssc sw r 50 a f m 80% = where m is the ramp rate of the slope-compensation signal, r cssc is the value of the resistor connected between cssc and cs used to program the ramp rate, and f sw is the switching frequency. error amplifier the max5974a/max5974b include an internal error amplifier with a sample-and-hold input. the feedback input of the max5974c/max5974d is continuously con - nected. the noninverting input of the error amplifier is connected to the internal reference and feedback is provided at the inverting input. high open-loop gain and unity-gain bandwidth allow good closed-loop bandwidth and transient response. calculate the power-supply out - put voltage using the following equation: fb1 fb2 out ref fb2 r r v v r + = where v ref = 1.52v for the max5974a/max5974b and v ref = 1.215v for the max5974c/max5974d. the amplifiers noninverting input is internally connected to a soft-start circuit that gradually increases the reference voltage during startup. this forces the output voltage to come up in an orderly and well-defined manner under all load conditions. applications information startup time considerations the bypass capacitor at in, c in , supplies current immediately after the devices wake up (see the typical application circuits ). large values of c in increase the startup time, but also supply gate charge for more cycles during initial startup. if the value of c in is too small, v in drops below 7v because ndrv does not have enough time to switch and build up sufficient voltage across the tertiary output (max5974c/max5974d) or coupled inductor output (max5974a/max5974b), which powers the device. the device goes back into uvlo and does not start. use a low-leakage capacitor for c in . typically, offline power supplies keep startup times to less than 500ms even in low-line conditions (85v ac input for universal offline or 36v dc for telecom applica - tions). size the startup resistor, r in , to supply both the maximum startup bias of the device (150 f a) and the charging current for c in . c in must be charged to 16v within the desired 500ms time period. c in must store enough charge to deliver current to the device for at least the soft-start time (t ss ) set by c ss . to calculate the approximate amount of capacitance required, use the following formula: g gtot sw in g ss in hyst i q f (i i )(t ) c v = + = where i in is the ics internal supply current (1.8ma) after startup, q gtot is the total gate charge for the n-channel and p-channel fets, f sw is the ics switch - ing frequency, v hyst is the bootstrap uvlo hysteresis (9v typ), and t ss is the soft-start time. r in is then cal - culated as follows: s(min) inuvr in start v v r i ? ? where v s(min) is the minimum input supply voltage for the application (36v for telecom), v inuvr is the boot - strap uvlo wake-up level (16v), and i start is the in supply current at startup (150 f a max).
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 22 choose a higher value for r in than the one calculated above if a longer startup time can be tolerated in order to minimize power loss on this resistor. active clamp circuit traditional clamp circuits prevent transformer saturation by channeling the magnetizing current (i m ) of the trans - former onto a dissipative rc network. to improve effi - ciency, the active clamp circuit recycles i m between the magnetizing inductance and clamp capacitor. v clamp is given by: s clamp v v 1 d ? = where v s is the voltage of the power source and d is the duty cycle. to select n-channel and p-channel fets with adequate breakdown voltages, use the maximum value of v clamp . v clamp(max) occurs when the input voltage is at its minimum and the duty cycle is at its maximum. v clamp(max-normal) during normal opera - tion is therefore: s(min) clamp(max-normal) p o s s(min) v v n v 1 n v ? = where v s(min) is the minimum voltage of the power source, n p /n s is the primary to secondary turns ratio, and v o is the output voltage. the clamp capacitor, n-channel, and p-channel fets must have breakdown voltages exceeding this level. if feed-forward maximum duty-cycle clamp is used then: dclmp min max-ff s dclmp2 dclmp1 dclmp2 v v d 1 2.43 2.43 v r 1 2.43 r r ? ? = = ? ? ? ? ? ? ? = ? ? ? + ? ? therefore, v clamp(max-ff) during feed-forward maxi - mum duty clamp is: ( ) s clamp(max-ff) max ff dclmp1 dclmp2 dclmp2 v v 1 d 2.43 r r r ? = ? + = the aux driver controls the p-channel fet through a level shifter. the level shifter consists of an rc network (formed by c aux and r aux ) and diode d5, as shown in the typical application circuits . choose r aux and c aux so that the time constant exceeds 100/f sw . diode d5 is a small-signal diode with a voltage rating exceeding 25v. additionally, c clamp should be chosen such that the complex poles formed with magnetizing inductance (l mag ) and c clamp are 2x to 4x away from the loop bandwidth: bw mag clamp 1-d 3 f 2 l c > bias circuit optocoupler feedback (max5974c/max5974d) an in-phase tertiary winding is needed to power the bias circuit when using optocoupler feedback. the voltage across the tertiary v t during the on-time is: t t out s n v v n = where v out is the output voltage and n t /n s is the turns ratio from the tertiary to the secondary winding. select the turns ratio so that v t is above the uvlo shutdown level (7.35v max) by a margin determined by the holdup time needed to ride through a brownout. coupled-inductor feedback (max5974a/max5974b) when using coupled-inductor feedback, the power for the devices can be taken from the coupled inductor dur - ing the off-time. the voltage across the coupled induc - tor, v coupled , during the off-time is: c coupled out o n v v n = where v out is the output voltage and n c /n o is the turns ratio from the coupled output to the main output winding. select the turns ratio so that v coupled is above the uvlo shutdown level (7.5v max) by a margin determined by the holdup time needed to ride through a brownout. this voltage appears at the input of the devices, less a diode drop. an rc network consisting of r snub and c snub is for damping the reverse recovery transients of diode d6.
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 23 during on-time, the coupled output is: s c coupled-on out s p o n n v (v v ) n n ? = ? where v s is the input supply voltage. care must be taken to ensure that the voltage at fb (equal to v coupled-on attenuated by the feedback resistive divider) is not more than 5v: ( ) fb2 fb-on coupled-on fb1 fb2 r v v 5v r r = < + if this condition is not met, a signal diode should be placed from gnd (anode) to fb (cathode). layout recommendations typically, there are two sources of noise emission in a switching power supply: high di/dt loops and high dv/dt surfaces. for example, traces that carry the drain current often form high di/dt loops. similarly, the heatsink of the main mosfet presents a dv/dt source; therefore, mini - mize the surface area of the mosfet heatsink as much as possible. keep all pcb traces carrying switching cur - rents as short as possible to minimize current loops. use a ground plane for best results. for universal ac input design, follow all applicable safety regulations. offline power supplies can require ul, vde, and other similar agency approvals. refer to the max5974a and max5974c evaluation kit data sheets for recommended layout and component values.
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 24 typical application circuits in en dclmp dt dither/ sync ss c in 1f 25v c f 330pf c comp2 6.8pf r in 100ki l2 6.8h c out1 c out2 c out3 c out4 c out5 0.1f c bulk 33f r dclmp1 30.1k i 1% pgood r opto2 1k i 1% r dclmp2 750 i 1% r dt 16.9k i 1% c ss 0.1f d1 d2 d3 n t l1 3.3m h t1 v s 36v to 57v in c dither 10nf ffb fb comp cs d5 auxdrv cssc gnd rt r ffb 10.0k i 1% r g1 121k i 1% r g2 200k i 1% r cssc 4.02k i 1% r aux 10k i r cs 0.2 i r gate3 10 i r gate4 10 i r gate1 10 i r gate2 10 i r fb1 7.5ki 1% 5v, 5a r fb2 2.49ki 1% n3 fds3692 n1 5i412dp u1 fod817csd n4 irf6217 n n p n s d4 n c aux 47nf c int 0.1f u2 tlv4314aidbvt-1.24v c clamp 47nf c comp1 2.2nf r opto1 825 i 1% r bias 4.02k i 1% r rt 14.7k i 1% r f 499 i 1% ndrv pgnd n2 5i412dp n r comp2 2.00k i 1% p r opto3 4.99k i 1% r comp2 499 i 1% max5974c max5974d (optocoupler feedback) r en 100k i
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 25 typical application circuits (continued) in en dclmp dt dither/ sync ss c in 1f 25v r in 100ki c out1 c out2 c out3 c out4 c out5 0.1f c bulk 33f 63v r dclmp1 30.1k i 1% r dclmp2 750 i 1% r dt 16.9k i 1% c ss 0.1f d3 d6 to fb 5v, 5a 4 x 47f 6.3v l coupled n c n o v s 36v to 57v c dither 10nf c int 47nf c comp 4.7nf ffb fb comp cs d5 auxdrv cssc gnd rt r ffb 10k i 1% r z 2k i 1% r cssc 4.02k i 1% r aux 10k i r cs 0.2 i r gate3 10 i r gate4 10 i r gate1 10 i r gate2 10 i r snub 69.8i 1% r fb1 54.9ki 1% r fb2 10ki 1% c snub 10pf n3 fds3692 n1 5i412dp n4 irf6217 n n p n s d4 n c aux 47nf c clamp 47nf r rt 14.7k i 1% ndrv pgnd n2 5i412dp n p max5974a max5974b (coupled inductor feedback) t1 c f 330pf r f 499 i 1% pgood r en 100k i
max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers 26 typical application circuits (continued) chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 tqfn-ep t1633+4 21-0136 90-0031 in en dclmp dt dither/ sync ss c in r in c out1 c out2 c out3 c out4 c bulk r dclmp1 r dclmp2 r dt r dither c ss d3 l2 v s c dither ffb fb comp c comp c hf cs d5 auxdrv cssc gnd rt r ffb r z r cssc r aux r cs r gate3 r gate4 r gate1 r gate2 n3 n1 n4 n n p t1 n s d4 n c aux c clamp r rt ndrv pgnd n2 n p max5974c max5974d d1 d2 n t l1 r fb1 r fb2 r en 100k i pgood
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 27 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max5974a/max5974b/max5974c/max5974d active-clamped, spread-spectrum, current-mode pwm controllers revision history revision number revision date description pages changed 0 6/10 initial release 1 9/10 introduced the max5974b/max5974d. updated the absolute maximum ratings , electrical characteristics , pin description , the p-channel mosfet gate driver , frequency foldback for high-efficiency light-load operation sections, and typical application circuits . 1, 2, 3, 12, 15, 17, 19, 21, 23, 24, 25 2 6/11 added internal zener diode information 1C10, 12C17, 19C25

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